Hierarchical DFT Approach for Testability

Abstract

The complexity and compactness of current chip designs have increased due to the rapid improvements in VLSI technology. To ensure that these designs function as intended, it is imperative that they can be tested after manufacture. After a chip is manufactured, defects can be found using Design for Testability (DFT) procedures, which eliminates the requirement for extensive functional testing on every one of the possibly many physical devices. Rather than testing each and every device in-depth, DFT optimizes the detection of problems by improving controllability and observability across all nodes within the system. To find problems on every single node, Automatic Test Pattern Generation (ATPG) was carried out on three distinct blocks in this project. WGLs that were created were used in simulations. All three blocks underwent Test Point Insertion (TPI), with the goal of enhancing the DC coverage. The outcomes of the three blocks were compared, an increase in pattern count along with a 0.4–2% improvement in DC coverage was observed.